{"id":3198,"date":"2021-01-29T03:12:00","date_gmt":"2021-01-29T09:12:00","guid":{"rendered":"https:\/\/patents.harnessip.com\/?p=3198"},"modified":"2022-01-30T21:48:51","modified_gmt":"2022-01-31T03:48:51","slug":"proper-claim-construction-is-essential-to-a-determination-of-patentabilty","status":"publish","type":"post","link":"https:\/\/patents.harnessip.com\/?p=3198","title":{"rendered":"Proper Claim Construction is Essential to a Determination of Patentabilty"},"content":{"rendered":"\n

In Intel Corp. v. Qualcomm Inc.<\/a>, [2020-1828, 2020-1867] (December 28, 2021), the Federal Circuit vacated the Board\u2019s decision that claims 1\u20139 and 12 of U.S. Patent No. 8,838,949 were not unpatentable, because the PTAB failed to tie its construction of the phrase \u201chardware buffer\u201d to the actual invention described in the specification. The Federal Circuit also vacated the Board’s decision that claims 16 and 17 were not unpatentable, because the Board failed to determine for itself whether there is sufficient corresponding structure in the specification to support the means-plus-function limitations in those claims to determine whether they are sufficiently definite to consider their validity. The ‘949 patent addresses a system with multiple processors, each of which must execute its own \u201cboot code\u201d to play its operational role in the system.<\/p>\n\n\n\n

The Federal Circuit said that it was clear from the claim language that “hardware buffer” has meaning, but it is unclear what that meaning was. The Federal Circuit said that there is no definition to be found in the intrinsic evidence, and the determination of that meaning depends on understanding what the intrinsic evidence makes clear is the substance of the invention\u2014what the inventor \u201cintended to envelop.\u201d The Federal Circuit concluded that the Board did not do enough to reach and articulate that understanding, and its claim construction is therefore wanting. The Federal Circuit explained that what was needed, then, was an analysis of the specification to arrive at an understanding of what it teaches about what a \u201chardware buffer\u201d is, based on both how it uses relevant words and its substantive explanations. In this crucial respect, the Board fell short in its analysis here, and we think the Board is better positioned
than we are to correct the deficiencies.<\/p>\n\n\n\n

The Federal Circuit noted that the Board\u2019s construction was entirely a negative one\u2014excluding \u201ctemporary\u201d buffers. The Federal Circuit said that although there is no per se rule against negative constructions, which in some cases can be enough to resolve the relevant dispute, the Board\u2019s construction in the present case was inadequate. It was not clear what precisely constitutes a
\u201ctemporary buffer\u201d as recited in the Board\u2019s construction.<\/p>\n\n\n\n

With respect to claims 16 and 17, there is no dispute that claim 16 (and hence dependent claim 17) contains terms that are in means-plus-function format governed by 35 U.S.C. \u00a7 112(f). Because Intel agreed with the Board\u2019s suggestion in the institution decision that two of the means-plus-function terms
in claim 16 were indefinite for lack of supporting structure, the Board concluded that Intel\u2019s statement necessarily meant that Intel, as the petitioner, had not met its burden to demonstrate the unpatentability of those claims. <\/p>\n\n\n\n

The Federal Circuit held that this was error and that a remand was required, because the Board did not
decide for itself whether required structure is present in the specification or whether, even if it was not, the absence of such structure precludes resolution of Intel\u2019s prior-art challenges. The Federal Circuit added that to avoid confusion going forward, the Board should, in IPRs where Impossibility because indefiniteness applies, clearly state that the final written decision does not include a determination of patentability of any claim that falls within the impossibility category.<\/p>\n","protected":false},"excerpt":{"rendered":"

In Intel Corp. v. Qualcomm Inc., [2020-1828, 2020-1867] (December 28, 2021), the Federal Circuit vacated the Board\u2019s decision that claims 1\u20139 and 12 of U.S. Patent No. 8,838,949 were not unpatentable, because the PTAB failed to tie its construction of … Continue reading →<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[57,7,26],"tags":[],"class_list":["post-3198","post","type-post","status-publish","format-standard","hentry","category-112f","category-claim-constructino","category-inter-partes-review"],"post_mailing_queue_ids":[],"_links":{"self":[{"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/posts\/3198","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=3198"}],"version-history":[{"count":1,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/posts\/3198\/revisions"}],"predecessor-version":[{"id":3199,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=\/wp\/v2\/posts\/3198\/revisions\/3199"}],"wp:attachment":[{"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=3198"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=3198"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/patents.harnessip.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=3198"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}